1. Field of the Invention
The present invention relates to semiconductor devices and methods of fabricating the same, and more particularly, to semiconductor devices having a recessed active edge and methods of fabricating the same.
2. Description of Related Art
Owing to the increased demand for highly integrated semiconductor devices, laborious research into minimizing the 2-dimensional sizes of components such as transistors has progressed. When a transistor is downscaled, the channel length and channel width also decrease. Because the driving current of the transistor is inversely proportional to the channel length and proportional to the channel width, a reduction in channel length can lead to a rise in driving current and an increase in the response speed. However, the reduction in the channel length may cause some problems, such as the occurrence of punch-through, which leads to a reduction in the driving current. For this reason, the channel width should be designed while considering the driving current required for operation of the semiconductor device.
FIG. 1 shows the layout of a conventional MOS transistor.
Referring to FIG. 1, the conventional MOS transistor includes an isolation layer 11 disposed in a predetermined region of a semiconductor substrate (not shown) to define an active region 13, 14, and 15. The active region 13, 14, and 15 includes a channel region 14, a source region 13, and a drain region 15. A gate electrode 17 is disposed to cross over the active region 13, 14, and 15. The channel region 14 is disposed under the gate electrode 17. Also, the channel region 14 has a channel length L1 and a channel width W1. The source region 13 is disposed on one side of the channel region 14, and the drain region 15 is disposed on the other side of the channel region 14. Source contact plugs 23, 24, and 25 are disposed on the source region 13, and drain contact plugs 26, 27, and 28 are disposed on the drain region 15. The source contact plugs 23, 24, and 25 are connected to a source interconnection (not shown), and the drain contact plugs 26, 27, and 28 are connected to a drain interconnection (not shown). When the MOS transistor includes a plurality of source contact plugs and a plurality of drain contact plugs, like the source drain contact plugs 23, 24, and 25 and the drain contact plugs 26, 27, and 28, contact resistance can be reduced.
For ease of illustration, the operation of the MOS transistor will hereinafter be described on the assumption that the MOS transistor is a PMOSFET. In this case, each of the source region 13 and the drain region 15 may be a P-type high-concentration impurity region, and the channel region 14 may be an N-type impurity region.
When an operating voltage equal to or higher than a threshold voltage is applied to the gate electrode 17 and a potential difference is generated between the source region 13 and the drain region 15, electron-hole pairs (EHPs) are generated by impact ionization in the channel region 14 near the drain region 15. Also, due to a field crowding effect, the impact ionization is accelerated on both edges of the channel region 14 under the gate electrode 17. In this case, the generated holes are transported to the drain region 15 due to the potential difference between the source region 13 and the drain region 15. On the other hand, some of the electrons generated by the impact ionization are trapped in the isolation layer 11. That is, electron traps 18 and 19 are formed in the isolation layer 11 near both edges of the channel region 14, respectively. When electrons trapped in the electron traps 18 and 19 increase, holes may accumulate at both edges of the channel region 14. These accumulated holes may function as extending regions 21 and 22 of the drain region 15. As a result, the extended drain regions 21 and 22 may reduce the effective channel length L1′ of the channel region 14. Consequently, both edges of the channel region 14 may become more susceptible to hot electron induced punch-through (HEIP).
In order to improve the foregoing problems, a method of extending the effective channel length by forming a protrusion on a gate electrode is provided.
FIG. 2 shows the layout of a conventional MOS transistor having a gate electrode protrusion.
Referring to FIG. 2, the conventional MOS transistor having a gate electrode protrusion includes an isolation layer 11 disposed in a predetermined region of a semiconductor substrate (not shown) to define an active region 13, 14, and 15. The active region 13, 14, and 15 includes a channel region 14, a source region 13, and a drain region 15. A gate electrode 37 is disposed to cross over the active region 13, 14, and 15. The gate electrode 37 includes protrusions 37T. The protrusions 37T of the gate electrode 37 are disposed on edges of the channel region 14. Source contact plugs 33 and 34 are disposed on the source region 13, and drain contact plugs 38 and 39 are disposed on the drain region 15. The source contact plugs 33 and 34 are connected to a source interconnection (not shown), and the drain contact plugs 38 and 39 are connected to a drain interconnection (not shown).
Owing to the protrusions 37T of the gate electrode 37, extended channel regions are formed on the edges of the channel region 14. That is, the edges of the channel region 14 have an extended effective channel length L2. The extended effective channel length L2 is longer than an original channel length L1 formed at other portions of the channel region 14. Thus, the protrusions 37T of the gate electrode 37 may serve to suppress the occurrence of HEIP.
However, the protrusions 37T of the gate electrode 37 should be formed in consideration of an insulation space between the source contact plugs 33 and 34 and the drain contact plugs 38 and 39. For example, a minimum distance D1 between the protrusions 37T of the gate electrode 37 and the drain contact plug 38 should be more than the resolution limit in a photolithography process. In this case, the space in which the source contact plugs 33 and 34 and the drain contact plugs 38 and 39 can be disposed on the source region 13 and the drain region 15 is reduced. When reducing the size or numbers of the source contact plugs 33 and 34 and the drain contact plugs 38 and 39, contact resistance may increase. The increase in the contact resistance deteriorates the current drivability of the MOS transistor.
Furthermore, a plurality of gate electrodes 37 may be disposed parallel to each other on the semiconductor substrate. In this case, the protrusions 37T of the gate electrode 37 should be formed in consideration of electrical insulation from protrusions (not shown) of other adjacent gate electrodes 37. This formation consideration with regard to the protrusions may further prevent high integration of the MOS transistor.
In order to overcome some of these problems, new transistors have been disclosed by Ichikawa in U.S. Pat. No. 6,611,027 B2 entitled “Protection Transistor with Improved Edge Structure.”
According to Ichikawa, new transistors having gate electrode protrusions may be provided. Nevertheless, it is necessary to develop improved transistors and methods of fabricating the same, which can extend an effective channel length on an edge of an active region.